View SCN2652_1735129.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SCN2652/scn68652 multi-protocol communications controller (mpcc) product specification ic19 data handbook 1995 may 01 integrated circuits
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 2 1995 may 01 853-1068 15179 description the SCN2652/68652 multi-protocol communications controller (mpcc) is a monolithic n-channel mos lsi circuit that formats, transmits and receives synchronous serial data while supporting bit-oriented or byte control protocols. the chip is ttl compatible, operates from a single +5v supply, and can interface to a processor with an 8 or 16-bit bidirectional data bus. applications ? intelligent terminals ? line controllers ? network processors ? front end communications ? remote data concentrators ? communication test equipment ? computer to computer links features ? dc to 2mbps data rate ? bit-oriented protocols (bop): sdlc, adccp, hdlc ? byte-control protocols (bcp): ddcmp, bisync (external crc) ? programmable operation 8 or 16-bit tri-state data bus error control crc or vrc or none character length 1 to 8 bits for bop or 5 to 8 bits for bcp sync or secondary station address comparison for bcp-bop idle transmission of sync/flag or mark for bcp-bop ? automatic detection and generation of special bop control sequences, i.e., flag, abort, ga ? zero insertion and deletion for bop ? short character detection for last bop data character ? sync generation, detection, and stripping for bcp ? maintenance mode for self-testing ? ttl compatible ? single +5v supply pin configuration pin function pin function 1nc 23nc 2ce 24a0 3 rxc 25 byte 4 rxsi 26 dben 5 s/f 27 db07 6 rxa 28 db06 7 rxda 29 db05 8 rxsa 30 db04 9 rxe 31 db03 10 gnd 32 db02 11 db08 33 db01 12 nc 34 nc 13 db09 35 db00 14 db10 36 v cc 15 db11 37 reset 16 db12 38 txa 17 db13 39 txbe 18 db14 40 txu 19 db15 41 txe 20 r /w 42 txsq 21 a2 43 txc 22 a1 44 mm 1 39 17 28 40 29 18 7 plcc 6 top view index corner note: db00 is least significant bit, highest number (that is, db15, a2) is most significant bit. 24 23 22 21 20 19 18 17 16 15 28 27 12 10 11 9 8 7 6 5 4 3 2 1 14 13 26 25 29 30 31 32 33 34 35 36 37 38 39 40 ce rxc rxsi s/f rxa rxda rxsa rxe gnd db08 db09 db10 db11 db12 db13 db14 db15 r /w a2 a1 a0 byte dben db07 db06 db05 db04 db03 db02 db01 db00 v cc reset txa txbe txu txe txsq txc mm dip top view sd00057 figure 1. pin configuration
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 3 ordering code v cc = 5v + 5% packages commercial 0 c to +70 c industrial -40 c to +85 c dwg # 40-pin ceramic dual in-line package (dip) SCN2652ac2f40 / scn68652ac2f40 0590b 40-pin plastic dual in-line package (dip) SCN2652ac2n40 / scn68652ac2n40 contact factory sot129-1 44-pin square plastic lead chip carrier (plcc) SCN2652ac2a44 / scn68652ac2a44 contact factory sot187-2 absolute maximum ratings 1 symbol parameter rating unit t a operating ambient temperature 2 note 4 c t stg storage temperature 65 to +150 c v cc all inputs with respect to gnd 3 0.3 to +7 v notes: 1. stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress ratin g only and functional operation of the device at these or at any other condition above those indicated in the operation sections of th is specification is not implied. 2. for operating at elevated temperatures the device must be derated based on +150 c maximum junction temperature. 3. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rate d maxima. 4. parameters are valid over operating temperature range unless otherwise specified. see ordering code table for applicable temp erature range and operating supply range. block diagram data bus buffer db15 db00 reset mm read/ write logic and control a2a0 byte r /w ce dben parameter control sync/address register 16 bits 16 pcsar internal bus receiver data/status register rdsr receiver logic and control 16 parameter control register 8 bits pcr v cc gnd transmitter data/status register tdsr transmitter logic and control 16 rxc rxsi txc txso s/f rxe rxa rxda rxsa txe txa txbe txu sd00058 figure 2. block diagram
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 4 pin description mnemonic pin no. type name and function db15db00 1710 2431 i/o data bus: db07db00 contain bidirectional data while db15db08 contain control and status information to or from the processor. corresponding bits of the high and low order bytes can be wire or'ed onto an 8-bit bus. the data bus is floating if either ce or dben are low. a2a0 1921 i address bus: a2a0 select internal registers. the four 16-bit registers can be addressed on a word or byte basis. see register address section. byte 22 i byte: single byte (8-bit) data bus transfers are specified when this input is high. a low level specifies 16-bit data bus transfers. ce 1 i chip enable: a high input permits a data bus operation when dben is activated. r /w 18 i read/write: r /w controls the direction of data bus transfer. when high, the data is to be loaded into the addressed register. a low input causes the contents of the addressed register to be presented on the data bus. dben 23 i data bus enable: after a2a0, ce, byte and r /w are set up, dben may be strobed. during a read, the 3-state data bus (db) is enabled with information for the processor. during a write, the stable data is loaded into the addressed register and txbe will be reset if tdsr was addressed. reset 33 i reset: a high level initializes all internal registers (to zero) and timing. mm 40 i maintenance mode: mm internally gates txso back to rxsi and txc to rxc for off line diagnostic purposes. the rxc and rxsi inputs are disabled and txso is high when mm is asserted. rxe 8 i receiver enable: a high level input permits the processing of rxsi data. a low level disables the receiver logic and initializes all receiver registers and timing. rxa 5 o receiver active: rxa is asserted when the first data character of a message is ready for the processor. in the bop mode this character is the address. the received address must match the secondary station address if the mpcc is a secondary station. in bcp mode, if strip-sync (pcsar 13 ) is set, the first non-sync character is the first data character; if strip-sync is zero, the character following the second sync is the first data character. in the bop mode, the closing flag resets rxa. in the bcp mode, rxa is reset by a low level at rxe. rxda* 6 o receiver data available: rxda is asserted when an assembled character is in rdsr l and is ready to be presented to the processor. this output is reset when rdsr l is read. rxc 2 i receiver clock: rxc (1x) provides timing for the receiver logic. the positive going edge shifts serial data into the rxsr from rxsi. s/f 4 o sync/flag: s/f is asserted for one rxc clock time when a sync or flag character is detected. rxsa* 7 o receiver status available: rxsa is asserted when there is a zero to one transition of any bit in rdsr h except for rsom. it is cleared when rdsr h is read. rxsi 3 i receiver serial input: rxsi is the received serial data. mark = `1', space = `0'. txe 37 i transmitter enable: a high level input enables the transmitter data path between tdsr l and txso. at the end of a message, a low level input causes txso = 1(mark) and txa = 0 after the closing flag (bop) or last character (bcp) is output on txso. txa 34 o transmitter active: txa is asserted after tsom (tdsr 8 ) is set and txe is raised. this output will reset when txe is low and the closing flag (bop) or last character (bcp) has been output on txso. txbe* 35 o transmitter buffer empty: txbe is asserted when thetdsr is ready to be loaded with new control information or data. the processor should respond by loading thetdsr which resets txbe. txu* 36 o transmitter underrun: txu is asserted during a transmit sequence when the service of txbe has been delayed for one character time. this indicates the processor is not keeping up with the transmitter. line fill depends on pcsar 11 . txu is reset by reset or setting of tsom (tdsr 8 ), synchronized by the falling edge of txc. txc 39 i transmitter clock: txc (1x) provides timing for the transmitter logic. the positive going edge shifts data out of the txsr to txso. txso 38 o transmitter serial output: txso is the transmitted serial data. mark = `1', space = `0'. v cc 32 i +5v: power supply. gnd 9 i ground: 0v reference ground. *indicates possible interrupt signal
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 5 table 1. register access registers no. of bits description* addressable pcsar parameter control sync/ address register 16 pcsar h and pcr contain parameters common to the receiver and transmitter. pcsar l contains a programmable sync character (bcp) or secondary station address (bop). pcr parameter control register 8 rdsr h contains receiver status information. rdsr receive data/status register 16 rdsr l = rxdb contains the received assembled character. tdsr transmit data/status register 16 tdsr h contains transmitter command and status information. tdsrl = txdb contains the character to be transmitted non-addressable ccsr control character shift register 8 hsr holding shift register 16 rxsr receiver shift register 8 these registers are used for character assembly (cssr txsr transmitter shift register 8 these registers are used for character assembly (cssr , hsr, rxsr ) , disassembl y ( txsr ) , and crc rxcrc receiver crc accumulation register 16 ,), y(), accumulation/generation (rxcrc, txcrc). txcrc transmitter crc generation register 16 notes: *h = high byte bits 158 l = low byte bits 70 table 2. error control character description fcs frame check sequence is transmitted/received as 16 bits following the last data character of a bop message. the divisor is usually crcccitt (x 16 + x 12 + x 5 + 1) with dividend preset to 1's but can be other wise determined by ecm. the inverted remainder is transmitter as the fcs. bcc block check character is transmitted/received as two successive characters following the last data character of a bcp message. the polynomial is crc16 (x 16 + x 15 + x 2 + 1) or crcccitt with dividend preset to 0's (as specified by ecm). the true remainder is transmitted as the bcc. table 3. special characters operation bit pattern function bop flag 01111110 frame message abort 11111111 generation terminate communication 01111111 detection ga 01111111 terminate loop mode repeater function address (pcsar l ) 1 secondary station address bcp sync (pcsar l ) or (txdb) 2 generation character synchronization notes: 1. ( ) = contents of. 2. for idle = 0 or 1 respectively. apa pcsar pcr rdsr tdsr 15 proto 14 ss/ga 13 sam 12 idle 11 e c m 10 98 s/ar 76 543210 txcl 15 14 13 12 11 rxcl 10 9 8 t x c l e r x c l e rerr 15 a b c 14 13 ror 12 rab/ ga 11 reom 10 9 8 rxdb rsom terr 15 not defined 14 13 tga 12 tabort 11 teom 10 9 8 txdb tsom note: refer to register formats for mnemonics and description. sd00059 figure 3. short form register bit formats
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 6 m u x rxsi from xmitter mm sel sync ff ccsr (8) sync/flag 1 comparator hsr (16) 8 8 m u x rxsr (8) to rdsr l bcp . crc bop . crc bcp . crc bop . crc zero (bop) deletion logic zero deletion control parity (bcp) logic m u x bcp bop rxcrc acc crc16 (bcp) or ccrcccitt (bop) crc16 = 0 comparator crcccit = f0b8 rerr receiver control logic rxc notes: 1. detected in sync ff and 7 ms bits of ccsr. 2. in bop mode, a minimum of two data characters must be received to turn the receiver active. reset rxe rxa rxda rxsa s/f 1-bit delay sd00060 figure 4. mpcc receiver data path txsr (8) m u x bop zero insertion logic zero insertion control trans- mitter control logic txc notes: 1. txcrc selected if teom = 1 and the last data character has been shifted out of txsr. 2. in bcp parity selected will be generated after each character is shifted out of txsr. reset txe txa txbe txu sd00088 txcrc acc (16) crc16 or crcccitt control character generator bcp parity generation flag abort ga sel 1, 2 sync ff 1 bit delay from tdsar l or pcsar l (sync) txso figure 5. mpcc transmitter data path
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 7 functional description the mpcc can be functionally partitioned into receiver logic, transmitter logic, registers that can be read or loaded by the processor, and data bus control circuitry. the register bit formats are shown in figure 3 while the receiver and transmitter data paths are depicted in figures 4 and 3. receiver operation general after initializing the parameter control registers (pcsar and pcr), the rxe input must be set high to enable the receiver data path. the serial data on the rxsi is synchronized and shifted into an 8-bit control character shift register (ccsr) on the rising edge of rxc. a comparison between ccsr contents and the flag (bop) or sync (bcp) character is made until a match is found. at that time, the s/f output is asserted for one rxc time and the 16-bit holding shift register (hsr) is enabled. the receiver then operates as described below. bop operation a flowchart of receiver operation in bop mode appears in figure 6. zero deletion (after five ones are received) is implemented on the received serial data so that a data character will not be interpreted as a flag, abort, or ga. bits following the flag are shifted through the ccsr, hsr, and into the receiver shift register (rxsr). a character will be assembled in the rxsr and transferred to the rdsr l for presentation to the processor. at that time the rxda output will be asserted and the processor must take the character no later than one rxc time after the next character is assembled in the rxsr. if not, an overrun (rdsr 11 = 1) will occur and succeeding characters will be lost. the first character following the flag is the secondary station address. if the mpcc is a secondary station (pcsar 12 = 1), the contents of rxsr are compared with the address stored in pcsar l . a match indicates the forthcoming message is intended for the station; the rxa output is asserted, the character is loaded into rdsr l , rxda is asserted and the receive start of message bit (rsom) is set. no match indicates that another station is being addressed and the receiver searches for the next flag. if the mpcc is a primary station, (pcsar 12 = 0), no secondary address check is made; rxa is asserted and rsom is set once the first non-flag character has been loaded into rdsr l and rxda has been asserted. extended address field can be supported by software if pcsar 12 = 0. when the 8 bits following the address character have been loaded into rdsr l and rxda has been asserted, rsom will be cleared. the processor should read this 8-bit character and interpret it as the control field. received serial data that follows is read and interpreted as the information field by the processor. it will be assembled into character lengths as specified by pcr 810 . as before, rxda is asserted each time a character has been transferred into rdsr l and is cleared when rdsr l is read by the processor. rdsr h should only be read when rxsa is asserted. this occurs on a zero to one transition of any bit in rdsr h except for rsom. rxsa and all bits in rdsr h except rsom are cleared when rdsr h is read. the processor should check rdsr 915 each time rxsa is asserted. if rdsr 9 is set, then rdsr 1215 should be examined. receiver character length may be changed dynamically in response to rxda: read the character in rxdb and write the new character length into rxcl. the character length will be changed on the next receiver character boundary. a received residual (short) character will be transferred into rxdb after the previous character in rxdb has been read, i.e. there will not be an overrun. in general the last two characters are protected from overrun. the crcccitt, if specified by pcsar 810 , is accumulated in rxcrc on each character following the flag. when the closing flag is detected in the ccsr, the received crc is in the 16-bit hsr. at that time, the receive end of message bit (reom) will be set; rxsa and rxda will be asserted. the processor should read the last data character in rdsr l and the receiver status in rdsr 915 . if rdsr 15 = 1, there has been a transmission error; the accumulated crcccitt is incorrect. if rdsr 1214 0, last data character is not of prescribed length. neither the received crc nor closing flag are presented to the processor. the processor may drop rxe or leave it active at the end of the received message. rxbcp operation the operation of the receiver in bcp mode is shown in figure 7. the receiver initially searches for two successive sync characters, of length specified by pcr 810 , that match the contents of pcsar l . the next non-sync character or next sync character, if stripping is not specified (pcsar 13 = 0), causes rxa to be asserted and enables the receiver data path. once enabled, all characters are assembled in rxsr and loaded into rdsr l . rxda is active when a character is available in rdsr l . rxsa is active on a 0 to 1 transition of any bit in rdsr h . the signals are cleared when rdsrl or rdsr h are read respectively. if crc16 error control is specified by pcsar 810 , the processor must determine the last character received prior to the crc field. when that character is loaded into rdsr l and rxda is asserted, the received crc will be in ccsr and hsr l . to check for a transmission error, the processor must read the receiver status (rdsr h ) and examine rdsr 15 . this bit will be set for one character time if an error free message has been received. if rdsr 15 = 0, the crc16 is in error. the state of rdsr 15 in bcp crc mode does not set rxsa. note that this bit should be examined only at the end of a message. the accumulated crc will include all characters starting with the first non-sync character if pcsar 13 = 1, or the character after the opening two syncs if pcsar 13 = 0. this necessitates external crc generation/checking when supporting ibm's bisync. this can be accomplished using the philips semiconductors scn2653 polynomial generator/checker. see typical applications. if vrc has been selected for error control, parity (odd or even) is regenerated on each character and checked when the parity bit is received. a discrepancy causes rdsr 15 to be set and rxsa to be asserted. this must be sensed by the processor. the received parity bit is stripped before the character is presented to the processor. when the processor has read the last character of the message, it should drop rxe which disables the receiver logic and initializes all receiver registers and timing.
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 8 assemble character in rxsr. zero deletion, accumulate crc if specified a initialize pcsar, pcr rxe = 1? receiver status bit 0 1 except rsom ? processor rxe = 1 no flag in ccsr* ? yes no * test made every rxc time no s/f = 1 for one rxc bit time (1) overrun (rovrn) causes loss of subsequent characters is it 1st character after flag ? no sec. station mode ? yes secondary station address is character = pcsar l ? no yes yes (pcsar 12 = 1) yes no flag in ccsr* ? yes end of message no rxsr rxdb no (pcsar 12 = 0) start of message rxa = 1 rsom = 1 for one character time rxda = 1 (processor should read rxdb) flag in ccsr* ? yes yes rxe 0 ? no a yes rxsa = 1 (processor should read and examine rdsr h reom, rab/ga, rovrn, abc, rerr) s/f = 1 for one rxc bit time reom = 1, rxa = 0 sd00061 figure 6. bop receive transmitter operation general after the parameter control registers (pcsar and pcr) have been initialized, txso is held at mark until tsom (tdsr 8 ) is set and txe is raised. then, transmitter operation depends on protocol mode. txbop operation transmitter operation for bop is shown in figure 8. a flag is sent after the processor sets the transmit start of message bit (tsom) and raises txe. the flag is used to synchronize the message that follows. txa will also be asserted. when txbe is asserted by the
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 9 mpcc, the processor should load tdsr l with the first character of the message. tsom should be cleared at the same time tdsr l is loaded (16-bit data bus) or immediately thereafter (8-bit data bus). flags are sent as long as tsom = 1. for counting the number of flags, the processor should reassert tsom in response to the assertion of txbe.all succeeding characters are loaded into tdsr l by the processor when txbe = 1. each character is serialized in txsr and transmitted on txso. internal zero insertion logic stuffs a a0o into the serial bit stream after five successive a1so are sent. this insures a data character will not match a flag, abort, or ga reserved control character. as each character is transmitted, the frame check sequence (fcs) is generated as specified by error control mode (pcsar 810 ). the fcs should be the crcccitt polynomial (x 16 + x 12 + x 5 + 1) preset to 1s. if an underrun occurs (processor is not keeping up with the transmitter), txu and terr (tdsr 15 ) will be asserted with abort or flag used as the txso line fill depending on the state of idle (pcsar 11 ). the processor must set tsom to reset the underrun condition. to retransmit the message, the processor should proceed with the normal start of message sequence. a residual character of 1 to 7 bits may be transmitted at the end of the information field. in response to txbe, write the residual character length into txcl and load txdb with the residual character. dynamic alteration of character length should be done in exactly the same sequence. the character length will be changed on the next transmit character boundary. after the last data character has been loaded into tdsr l and sent to txsr (txbe = 1), the processor should set teom (tdsr 9 ). the mpcc will finish transmitting the last character followed by the fcs and the closing flag. the processor should clear teom and drop txe when the next txbe is asserted. this corresponds to the start of closing flag transmission. when txe has been dropped. txa will be low 1 1/2 bit times after the last bit of the closing flag has been transmitted. txso will be marked after the closing flag has been transmitted. if txe and teom are high, the transmitter continues to send flags. the processor may initiate the next message by resetting teom and setting tsom, or by loading tdsr l with a data character and then simply resetting tsom (without setting tsom). txbcp operation transmitter operation for bcp mode is shown in figure 9. txa will be asserted after tsom = 1 and txe is raised. at that time sync characters are sent from pcsar l or tdsr l (idle = 0 or 1) as long as tsom = 1. txbe is asserted at the start of transmission of the first sync character. for counting the number of syncs, the processor should reassert tsom in response to the assertion of txbe. when tsom = 0 transmission is from tdsr l , which must be loaded with characters from the processor each time txbe is asserted. if this loading is delayed for more than one character time, an underrun results: txu and terr are asserted and the txso line fill depend on idle (pcsar 11 ). the processor must set tsom and retransmit the message to recover. this is not compatible with ibm's bisync, so that the user must not underrun when supporting that protocol. crc16, if specified by pcsar 810 , is generated on each character transmitted from tdsr l when tsom =0. the processor must set teom = 1 after the last data character has been sent to txsr (txbe = 1). the mpcc will finish transmitting the last data character and the crc16 field before sending sync characters which are transmitted as long as teom = 1. if syncs are not desired after crc16 transmission, the processor should clear teom and lower txe when the txbe corresponding to the start of crc16 transmission is asserted. when teom = 0, the line is marked and a new message may be initiated by setting tsom and raising txe. if vrc is specified, it is generated on each data character and the data character length must not exceed 7 bits. for software lrc or crc, teom should be set only if sync's are required at the end of the message block. special case: the capability to transmit 16 spaces is provided for line turnaround in half duplex mode or for a control recovery situation. this is achieved by setting tsom and teom, clearing teom when txbe = 1, and proceeding as required. programming prior to initiating data transmission or reception, pcsar and pcr must be loaded with control information from the processor. the contents of these registers (see register format section) will configure the mpcc for the user's specific data communication environment. these registers should be loaded during power-on initialization and after a reset operation. they can be changed at any time that the respective transmitter or receiver is disabled. the default value for all registers is zero. this corresponds to bop, primary station mode, 8-bit character length, fcs = crcccitt preset to 1s. for bop mode the character length register (pcr) may be set to the desired values during system initialization. the address and control fields will automatically be 8-bits. if a residual character is to be transmitted, txcl should be changed to the residual character length prior to transmission of that character. data bus control the processor must set up the mpcc register address (a2a0), chip enable (ce), byte select (byte), and read/write (r /w) inputs before each data bus transfer operation. during a read operation (r /w = 0), the leading edge of dben will initiate an mpcc read cycle. the addressed register will place its contents on the data bus. if byte = 1, the 8-bit byte is placed on db1508 or db0700 depending on the h/l status of the register addressed. unused bits in rdsr l are zero. if byte = 0, all 16 bits (db1500) contain mpcc information. the trailing edge of dben will reset rxda and/or rxsa if rdsr l or rdsr h is addressed respectively. dben acts as the enable and strobe so that the mpcc will not begin its internal read cycle until dben is asserted. during a write operation (r /w = 1), data must be stable on db 1508 and/or db 0700 prior to the leading edge of dben. the stable data is strobed into the addressed register by dben. txbe will be cleared if the addressed register was tdsr h or tdsr l .
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 10 assemble character in rxsr, strip vrc if specified, accumulate crc if specified a initialize pcsar, pcr rxe = 1? any receiver status bit 0 1 ? processor rxe = 1 no sync detect 1 in ccsr? yes no s/f = 1 for one rxc bit time (1) syncs are assembled (2) overrun (rovrn) causes loss of subsequent characters strip sync (pcsar 13 ) = 1? no no rxsr rxdb rxsa = 1 (processor should read and examine rdsr h rovrn, rerr (if vrc specified) rxda = 1 (processor should read rxdb) yes sync detect 2 in ccsr? no sync detect in ccsr? yes yes yes no rxa = 1 yes rxe = 0? yes no a rxe = 0 when last character has been serviced notes: 1. test made every rxc time. 2. test made on rx character boundary. sd00062 figure 7. bcp receive
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 11 tsom txe = 1? a initialize pcsar, pcr, tdsr h (processor must clear tabort/ga in response to txbe = 1) txso = mark no tsom = 1 txe = 1 yes b txa = 1 transmit flag on txso tsom = 0? no txbe = 1 processor should load txdb and tsom = 0) yes (processor may set tabort, tga, as required) tabort = 1? yes no txso = abort = 1 1111111 if idle = 0 flag = 01 111110 if idle = 1 under run? yes no txso = abort if idle = 0 flag if idle = 1 tsom = 1? yes b no serialize data character in txdb, zero insertion, accumulate crc if specified by ecm, transmit on txso on underrun: txu = 1, terr = 1 (processor should set tsom) txbe = 1 (processor should load txdb with next data char) teom = 1? yes transmit accumulated fcs (if specified) as inverted remainder no transmit flag on txso* no teom = 0? txbe = 1 tsom = 1? yes b yes no txe = 0? yes a txa = 0 no * ga will be transmitted if tga is set together with teom. (processor should reset teom and set tsom or drop txe) sd00063 figure 8. bop transmit
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 12 yes tsom, txe = 1? txso = mark initialize pcsar, pcr, tdsr h a no tsom = 1 txe = 1 b txa = 1 transmit sync on txso sync from pcsar l idle = 0 sync from txdb idle = 1 tsom = 0? txbe = 1 no after sync(s), processor loads data character in txdb and tsom = 0 yes serialize data character in txdb, generate vrc or accumulate crc as specified, transmit on txso txbe = 1 (processor should load txdb) teom = 1? c no (processor should get teom at end of message if crc specified) under- run? no yes txso = sync from pcsar l if idle = 0 mark if idle = 1 until tsom = 1 txu = 1, terr = 1 (processor should set tsom = 1) yes b transmit accumulated crc specified (if no crc, teom should = 0) txbe = 1 (processor should clear teom and drop txe) teom = 0? txso = sync or txdb depending on idle bit no yes c txe = 0? no yes a txa = 0 processor sd00064 figure 9. bcp transmit
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 13 table 4. mpcc register addressing a2 a1 a0 register byte = 0 (16-bit data bus = db 15 db 00 ) 0 0 x rdsr 0 1 x tdsr 1 0 x pcsar 1 1 x pcr* byte = 1 (8-bit data bus = db 70 or db 158 **) 0 0 0 rdsr l 0 0 1 rdsr h 0 1 0 tdsr l 0 1 1 tdsr h 1 0 0 pcsar l 1 0 1 pcsar h 1 1 0 pcr l * 1 1 1 pcr h notes: * pcr lower byte does not exist. it will be all a0os when read. ** corresponding high and low order pins must be tied together. table 5. parameter control register (pcr)(r/w) bit name mode function 0007 not defined 0810 rxcl bop/bcp receiver character length is loaded by the processor when rxcle = 0. the character length is valid after transmission of single byte address and control fields have been received. 10 9 8 char length (bits) 000 8 001 1 010 2 011 3 100 4 101 5 110 6 111 7 11 rxcle bop/bcp receiver character length enable should be zero when the processor loads rxcl. the remaining bits of pcr are not affected during loading. always 0 when read. 12 txcle bop/bcp transmitter character length enable should be zero when the processor loads txcl. the remaining bits of pcr are not affected during loading. always 0 when read. 1315 txcl bop/bcp transmitter character length is loaded by the processor when txcle = 0. character bit length specification format is identical to rxcl. it is valid after transmission of single byte address and control fields.
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 14 table 6. parameter control sync/address register (pcsar)(r/w) bit name mode function 0007 s/ar bop sync/address register. contains the secondary station address if the mpcc is a secondary station. the contents of this register is compared with the first received non-flag character to determine if the message is meant for this station. bcp sync character is loaded into this register by the processor. it is used for receive and transmit bit synchronization with bit length specified by rxcl and txcl. 0810 ecm bop/bcp error control mode 10 9 8 suggested mode char. length crcccitt preset to 1's 0 0 0 bop 18 crcccitt preset to 0's 0 0 1 bcp 8 not used 0 1 0 crc16 preset to 0's 0 1 1 bcp 8 vrc odd 1 0 0 bcp 57 vrc even 1 0 1 bcp 57 not used 1 1 0 no error control 1 1 1 bcp/bop 58 ecm should be loaded by the processor during initialization or when both data paths are idle. 11 idle determines line fill character to be used if transmitter underrun occurs (txu asserted and terr set) and transmission of special characters for bop/bcp. bop idle = 0, transmit abort characters during underrun and when tabort = 1. idle = 1, transmit flag characters during underrun and when tabort = 1. bcp idle = 0 transmit initial sync characters and underrun line fill characters from thes/ar. idle = 1 transmit initial sync characters from txdb and marks txso during underrun. 12 sam bop secondary address mode = 1 if the mpcc is a secondary station. this facilitates automatic recognition of the received secondary station address. when transmitting, the processor must load the secondary address into txdb. sam = 0 inhibits the received secondary address comparison which serves to activate the receiver after the first non-flag character has been received. 13 ss/ga strip sync/go ahead. operation depends on mode. bop ss/ga = 1 is used for loop mode only and enables ga detection. when a ga is detected as a closing character, reom and rab/ga will be set and the processor should terminate the repeater function. ss/ga = 0 is the normal mode which enables abort detection. it causes the receiver to terminate the frame upon detection of an abort or flag. bcp ss/ga = 1, causes the receiver to strip sync's immediately following the first two sync's detected. sync's in the middle of a message will not be stripped. ss/ga = 0, presents any sync's after the initial two sync's to the processor. 14 proto determines mpcc protocol mode bop proto = 0 bcp proto = 1 15 apa bop all parties address. if this bit is set, the receiver data path is enabled by an address field of `11111111' as well as the normal secondary station address.
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 15 table 7. transmit data/status register (tdsr) (r/w except tdsr15) bit name mode function 0007 txdb bop/bcp transmit data buffer. contains processor loaded characters to be serialized in txsr and transmitted on txso. 08 tsom transmitter start of message. set by the processor to initiate message transmission provided txe = 1. bop tsom = 1 generates flags. when tsom = 0 transmission is from txdb and fcs generation (if specified) begins. fcs, as specified by pcsar 810 , should be crcccitt preset to 1's. bcp tsom = 1 generates syncs from pcsar l or transmits from txdb for idle = 0 or 1 respectively. when tsom = 0 transmission is from txdb and crc generation (if specified) begins. 09 teom transmit end of message. used to terminate a transmitted message. bop teom = 1 causes the fcs and the closing flag to be transmitted following the transmission of the data character in txsr. flags are transmitted until teom = 0. abort or ga are transmitted if tabort or tga are set when teom = 1. bcp teom = 1 causes crc16 to be transmitted (if selected) followed by syncs from pcsar l or txdb (idle = 0 or 1). clearing teom prior to the end of crc16 transmission (when txbe = 1) causes txso to be marked following the crc16. txe must be dropped before a new message can be initiated. if crc is not selected, teom should not be set. 10 tabort bop transmitter abort = 1 will cause abort or flag to be sent (idle = 1 or 1) after the current character is transmitted. (abort = 1 1111111) 11 tga bop transmit go ahead (ga) instead of flag when teom = 1. this facilitates repeater termination in loop mode. (ga = 01 111111) 1214 not defined 15 terr read only transmitter error = 1 indicates the txdb has not been loaded in time (one character time1/2 txc period after txbe is asserted) to maintain continuous transmission. txu will be asserted to inform the processor of this condition. terr is cleared by setting tsom. see timing diagram. bop abort's or flag's are sent as fill characters (idle = 0 or 1) bcp sync's or mark's are sent as fill characters (idle = 0 or 1). for idle = 1 the last character before underrun is not valid.
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 16 table 8. receiver data/status register (rdsr)(read only) bit name mode function 0007 rxdb bop/bcp receiver data buffer. contains assembled characters from the rxsr. if vrc is specified, the parity bit is stripped. 08 rsom bop receiver start of message = 1 when a flag followed by a non-flag has been received and the latter character matches the secondary station if sam = 1. rxa will be asserted when rsom = 1. rsom resets itself after one character time and has no affect on rxsa. 09 reom bop receiver end of message = 1 when the closing flag is detected and the last data character is loaded into rxdb or when an abort/ga character is received. reom is cleared on reading rdsr h , reset operation, or dropping of rxe. 10 rab/ga bop received abort or ga character = 1 when the receiver senses an abort character if ss/ga = 0 or a ga character if ss/ga = 1. rab/ga is cleared on reading rdsr h , reset operation, or dropping of rxe. a received abort does not set rxda. 11 ror bop/bcp receiver overrun = 1 indicates the processor has not read last character in the rxdb within one character time + 1/2 rxc period after rxda is asserted. subsequent characters will be lost. ror is cleared on reading rdsr h , reset operation, or dropping of rxe. 1214 abc bop assembled bit count. specifies the number of bits in the last received data character of a message and should be examined by the processor when reom = 1(rxda and rxsa asserted). abc = 0 indicates the message was terminated (by a flag or ga) on a character boundary as specified by pcr 810 . otherwise, abc = number of bits in the last data character. abc is cleared when rdsr h is read, reset operation, or dropping rxe. the residual character is right justified inrdsr l . 15 rerr bop/bcp receiver error indicator should be examined by the processor when reom = 1 in bop, or when the processor determines the last data character of the message in bcp with crc or when rxsa is set in bcp with vrc. crcccitt preset to 1's/0's as specified by pcsar 810 : rerr = 1 indicates fcs error (crc f0b8 or 0) rerr = 0 indicates fcs received correctly (crc = f0b8 or = 0) crc16 preset to 0's on 8-bit characters specified by pscar 810 : rerr = 1 indicates crc16 received correctly (crc = 0). rerr = 0 indicates crc16 error (crc 0) vrc specified by pcsar 810 : rerr = 1 indicates vrc error rerr = 0 indicates vrc is correct. dc electrical characteristics 1, 2 parameter test conditions limits unit parameter test conditions min typ max unit input voltage v il low 0.8 v v ih high 2.0 output voltage v ol low i ol = 1.6ma 0.4 v v oh high i oh = 100 m a 2.4 i cc power supply current v cc = 5.25v, t a = 0 c 150 ma leakage current i il input v in = 0 to 5.25v 10 m a i ol output v out = 0 to 5.25v 10 capacitance c in input v in = 0v, f = 1mhz 20 pf c out output v out = 0v, f = 1mhz 20
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 17 ac electrical characteristics 1, 2, 3 parameter 2mhz clock unit parameter min typ max unit set-up and hold time t acs address/control set-up 50 t ach address/control hold 0 t ds data bus set-up (write) 50 ns t dh data bus hold (write) 0 t rxs receiver serial data set-up 150 t rxh receiver serial data hold 150 pulse width t res reset 250 ns t dben dben 250 m 4 delay time t dd data bus (read) 170 ns t txd transmit serial data 250 ns t dbend dben to dben delay 200 t df data bus float time (read) 150 ns f clock (rxc, txc) frequency 2.0 mhz t clk1 clock high (mm = 0) 165 t clk2 clock high (mm = 1) 240 ns t clk0 clock low 240 notes: 1. parameters are valid over operating temperature range unless otherwise specified. see ordering code table for applicable temp erature range and operating supply range. 2. all voltage measurements are referenced to ground. all time measurements are at 0.8v or 2.0v. input voltage levels for testi ng are 0.4v and 2.4v. 3. output load c l = 100pf. 4. m = txc low and applies to writing to tdsr h only. timing diagrams reset t res reset reset and write data bus t dben t acs dben a 0 , a 2 t ach t acs t ach ce, r /w, byte t df t dd floating valid valid floating not d 0 d 15 (read) t ds t dh d 0 d 15 (write) sd00065 figure 10. timing diagrams
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 18 timing diagrams (continued) clock t clk1 1/f txc txso t clk0 txd rxc rxsi t clk0 t clk1 t rxs t rxh sd00066 figure 11. timing diagrams (cont.) transmit start of message txc sync/flag 1 1st char 8 txc 1 mark txso txbe dben set tsom load 1st char reset tsom load 2nd char txe txa 2 3 notes: 1. sync may be 5 to 8 bits and will contain parity bit as specified. 2. txa goes high relative to txc rising edge after tsom has been set and txe has been raised. 3. txbe goes low relative to dben falling edge on the first write transfer into tdsr. it is reasserted 1 txc time before the fir st bit of the transmitted sync/flag. txbe then goes low relative to dben falling edge when writing into tdsr h and/or tdsr l . it is reasserted on the rising edge of the txc that corresponds to the transmission of the last bit of each character, except in bop mode when the crc is to be sent as the next character (see transmit timingend of message). sd00067 figure 12. timing diagrams (cont.)
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 19 timing diagrams (continued) transmit end of bop message txc mark txso dben load last char set teom reset teom txe 2 txa 3 notes: 1. txbe goes low relative to the falling edge of dben corresponding to loading tdsr h/l . it goes high one txc before character transmission begins and also when txa has been dropped. 2. txe can be dropped before resetting teom if txbe (corresponding to the closing flag) is high. alternatively txe can remain hi gh and a new message initiated. 3. txa goes low after txe has been dropped and 1 1/2 txc's after the last bit of the closing flag has been transmitted. flag crc last char next to last char txbe 1 sd00068 figure 13. timing diagrams (cont.) transmit timing end of bcp message txc mark txso dben load last char set teom reset teom txe txa note: 1. when SCN2652 generated crc is not required. teom should only be set if syncs are to follow the message block. in that case, t xe should be dropped in response to txbe (which corresponds to the start of transmission of the last character). when crc is required, txe must be dropped before crc tr ansmission is complete. otherwise, the contents of txdb will be shifted out on txso. this facilitates transmission of contiguous messages. crc 1 last char next to last char txbe sd00069 figure 14. timing diagrams (cont.)
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 20 timing diagrams (continued) transmit underrun txc dben 2 set tsom notes: 1. txu goes active relative to txc falling edge if txbe has not been serviced after n-1/2 txc times (where n = transmit characte r length). txu is reset on the txc falling edge follow- ing assertion of the tsom command. 2. an underrun will occur at the next character boundary if teom is reset and the transmitter remains enabled, unless the tsom c ommand is asserted or a character is loaded into the txdb. txu 1 sd00070 figure 15. timing diagrams (cont.) receive start of message rxc rxa rxda 2 dben 1st char read 2nd char read s/f 3 rxe notes: 1. rxa goes high relative to falling edge of rxc when rxe is high and: a. a data character following two sync's is in rxdb (bcp mode). b. character following flag is in rxdb (bop primary station mode). c. character following flag is in rxdb and character matches the secondary station address or all p arties address (bop secondary station mode). 2. rxda goes high on rxc falling edge when a character in rxdb is ready to be read. it comes up before rxsa and goes low on the falling edge of dben when rxdb is read. 3. s/f goes high relative to rising edge of rxc anytime a sync (bcp) or flag (bop) is detected. 1 1st char ready to be read 2nd char ready to be read sd00071 figure 16. timing diagrams (cont.)
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 21 timing diagrams (continued) receive end of message rxc rxda dben (8-bit) read data read status rxe 2 rxa 3 notes: 1. at the end of a bop message, rxsa goes high when flag detection (s/f 1) forces reom to be set. processor should read the last data character (rdsr l ) and status (rdsr h ) which resets rxda and rxsa respectively. for bcp end of message, rxsa may not be set and s/f = 0. the processor should read the last data character and status. 2. rxe must be dropped for bcp with non-contiguous messages. it may be left on at the end of a bop message (see bop receive oper ation). 3. rxa is reset relative to the falling edge of rxc after the closing flag of a bop message (reom = 1 and rxsa active.) or when rxe is dropped. rxsa 1 s/f sd00072 figure 17. timing diagrams (cont.) typical applications SCN2652 mpcc microprocessor interface notes: 1. possible m p interrupt requests are: rxda rxsa txbe txu 2. other SCN2652 status signals and possible uses are s f line idle indicator, frame delimiter. rxa handshake on rxe, line turn around control. txa handshake on txe, line turn around control. 3. line drivers/receivers (ld/lr) convert eia to ttl voltages and vice-versa. 4. rts should be dropped after the crc (bcp) or flag (bop) has been transmitted. this forces cts low and txe low. 5. corresponding high and low order bits of db must be or tied. reset clock 8-bit m p f data bus address control ts buffer modem control logic status mpcc SCN2652 db0db7 a2a0, r /w dben ce a1o byte rxe txe dcd cts lr txc synchro- nous modem lr rxc ld txso lr rxsi rts, cts, dtr, dsr, dcd reset sd00073 figure 18. typical applications
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 22 typical applications (continued) dma/processor interface for non-dma operation txbe and rxda are set to the processor which then loads or reads data characters as required. dma controller word count address ptr r/w control rdreq address r /w controls SCN2652 address and control SCN2652 rxa wrreq to processor rxda db15db00 txbe a2a0 byte r /w ce dben rxc txc rxsi txso modem or dce data bus system address and control bus processor (p) and support logic: db15db00 address, r /w, control rxe rxsa txa txe txu s/f reset mm rxda txbe 1. initializes SCN2652 2. sets/resets tsom, teom 3. responds to rxsa 8 or 16 bits r /w memory data bus address, ce, r /w sd00074 figure 19. typical applications (cont.) channel interface computer or terminal lr mpcc SCN2652 txc baud rate generator rxc ld ld lr lr ld ld lr txso rxsi mpcc SCN2652 txc baud rate generator rxc txso rxsi computer or terminal no modem dc baseband transmission sd00075 figure 20. typical applications (cont.)
philips semiconductors product specification SCN2652/scn68652 multi-protocol communications controller (mpcc) 1995 may 01 23 SCN2652/scn2653 interface typical protocols: bisync, ddcmp, sdlc, hdlc cpu interrupts txbe, txu, rxda, rxsa db7db0 mpcc SCN2652 a2 a1 a0 r /w dben ce txd rxd txc rxc pgc scn2653 ce0 a1 r /w a0 ce1 db7db0 int (open drain) 5v sd00076 figure 21. typical applications (cont.)
philips semiconductors product specification SCN2652/scn68562 multi-protocol communications controller (mpcc) 1998 may 01 24 0590b 40-pin (600 mils wide) ceramic dual in-line (f) package (with window (fa) package) notes: 1. controlling dimension: inches. millimeters are 2. dimension and tolerancing per ansi y14. 5m-1982. 3. ato, ado, and aeo are reference datums on the body 4. these dimensions measured with the leads 5. pin numbers start with pin #1 and continue 6. denotes window location for eprom products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane t. counterclockwise to pin #40 when viewed shown in parentheses. from the top. d pin # 1 e 0.225 (5.72) max. 0.010 (0.254) te d 0.023 (0.58) 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) t seating plane 0.620 (15.75) 0.590 (14.99) (note 4) 0.598 (15.19) 0.571 (14.50) bsc 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (note 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) bsc 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) see note 6 8530590b 06688
philips semiconductors product specification SCN2652/scn68562 multi-protocol communications controller (mpcc) 1998 may 01 25 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification SCN2652/scn68562 multi-protocol communications controller (mpcc) 1998 may 01 26 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification SCN2652/scn68562 multi-protocol communications controller (mpcc) 1998 may 01 27 notes
philips semiconductors product specification SCN2652/scn68562 multi-protocol communications controller (mpcc) 1998 may 01 28 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 08-98 document order number:
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

▲Up To Search▲

Price & Availability of SCN2652

	To Download SCN2652 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .